FPGA/verilog-ethernet
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4 Commits

Author SHA1 Message Date
Alex Forencich
47ca9a8725 Replace eth_crc modules for generic lfsr module 2016-06-28 17:31:58 -07:00
Alex Forencich
9c01e114b4 Happy new year 2016-01-05 00:34:32 -08:00
Alex Forencich
ec95a6055d Feed through and synchronize FIFO status signals 2015-05-12 19:12:23 -07:00
Alex Forencich
00a87b26b3 Add FIFO wrapper for 10G MAC module 2015-05-08 00:07:09 -07:00