FPGA/verilog-ethernet
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2 Commits

Author SHA1 Message Date
Alex Forencich
625c48c59c Add transceiver reset watchdog 2021-10-17 20:19:04 -07:00
Alex Forencich
8b95b33bab Add cocotb testbench for 10G PHY 2021-10-15 01:07:26 -07:00