FPGA/verilog-ethernet
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6 Commits

Author SHA1 Message Date
Alex Forencich
92681fad8c Add DROP_OVERSIZE_FRAME parameter 2021-08-25 22:56:22 -07:00
Alex Forencich
ede73b434a Add PIPELINE_OUTPUT parameter to FIFO adapter modules 2020-09-07 00:22:55 -07:00
Alex Forencich
ce00df8de1 Include instance names in error messages 2019-07-25 16:30:10 -07:00
Alex Forencich
c5f44c70d1 Add parameter documentation 2019-07-24 13:54:21 -07:00
Alex Forencich
69de6fd2a4 Convert FIFOs to use DEPTH parameter instead of ADDR_WIDTH 2019-07-18 11:27:25 -07:00
Alex Forencich
8e969aa14c Add FIFO/width adapter wrapper modules 2019-04-26 18:38:25 -07:00