FPGA/verilog-ethernet
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2 Commits

Author SHA1 Message Date
Alex Forencich
5d349c9cb2 Enable overtemp shutdown in constraints files 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-21 18:17:12 -07:00
Alex Forencich
ea80d853ed Use unified 10G/25G design for Alveo U250 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 19:53:21 -07:00