FPGA/verilog-ethernet
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8 Commits

Author SHA1 Message Date
Alex Forencich
e542d39a75 Fix assignment type 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-20 09:21:34 -07:00
Alex Forencich
c1e947dc3d Timing optimization of PTP modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-22 22:57:44 -07:00
Alex Forencich
db881ed551 Remove magic numbers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-22 18:39:21 -07:00
Alex Forencich
945f22fd33 Add output pipeline to PTP clock module 2022-03-27 23:46:49 -07:00
Alex Forencich
0f2db26a8e Simplify logic in PTP clock module 2022-03-16 19:01:00 -07:00
Alex Forencich
6b18e56cb1 Add default_nettype none and resetall directives 2021-10-20 17:29:12 -07:00
Alex Forencich
1dd349399b PTP clock period is always positive 2021-03-17 21:13:36 -07:00
Alex Forencich
e181ea5abc Add PTP clock module and testbench 2019-06-03 19:00:28 -07:00