FPGA/verilog-ethernet
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6 Commits

Author SHA1 Message Date
Alex Forencich
585ccefa15 Add TX underflow error signal 2019-03-26 12:42:08 -07:00
Alex Forencich
20017c04b9 Work around MyHDL cosimulation race condition 2018-10-30 11:58:53 -07:00
Alex Forencich
2e9602b5b4 Update testbenches to use wait 2018-07-02 18:20:07 -07:00
Alex Forencich
e4672915e6 Update testbenches to use instances() 2018-06-13 22:43:11 -07:00
Alex Forencich
0fd157964a Happy new year 2018-02-26 12:50:51 -08:00
Alex Forencich
bb9e789645 Update GMII PHY interface and add GMII MAC wrappers 2017-05-31 18:40:18 -07:00