FPGA/verilog-ethernet
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2 Commits

Author SHA1 Message Date
Alex Forencich
50b6f53387 Update testbench clock frequencies 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-15 01:53:31 -07:00
Alex Forencich
0b18633bb1 Use unified 10G/25G design for Alveo U200 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 19:49:25 -07:00