FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-28 07:03:08 +08:00
Code Issues Projects Releases Wiki Activity
190 Commits 1 Branch 0 Tags
Commit Graph

11 Commits

Author SHA1 Message Date
Alex Forencich
c5837daa2f Update testbenches to use instances() 2018-06-13 22:26:10 -07:00
Alex Forencich
5df7efe516 Happy new year 2018-02-26 12:25:20 -08:00
Alex Forencich
b00eaf4d3c Add tkeep signal and update testbench for stat counter 2017-11-21 00:17:42 -08:00
Alex Forencich
aebe0549dd Happy new year 2017-05-18 13:35:11 -07:00
Alex Forencich
5fa36eeaa7 Rework endpoints, update testbenches 2016-09-12 13:38:34 -07:00
Alex Forencich
be4034071b Happy new year 2016-01-05 00:24:20 -08:00
Alex Forencich
02a7f4d5ed Update testbenches to python 3 2015-03-21 03:32:19 -07:00
Alex Forencich
ac2f7e546d Adjust syntax for old Python 2 2014-11-05 16:40:27 -08:00
Alex Forencich
e8c43653e3 Adjust syntax for old Python 2 2014-11-05 16:33:33 -08:00
Alex Forencich
67bb09ba42 Add busy output to statistics collection module 2014-10-21 16:09:55 -07:00
Alex Forencich
f22381baa2 Initial commit of basic statistics collection module 2014-10-21 13:20:37 -07:00