FPGA/verilog-ethernet
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2 Commits

Author SHA1 Message Date
Alex Forencich
77ecbd7dcb Makefile updates 2016-10-05 17:41:00 -07:00
Alex Forencich
eb8dd775a1 Add 10G reference design for DE5-Net 2016-01-25 00:53:06 -08:00