FPGA/verilog-ethernet
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4 Commits

Author SHA1 Message Date
Alex Forencich
c2e459c971 Connect transceiver control lines 2017-03-09 17:14:14 -08:00
Alex Forencich
270641b7a3 Update UDP modules and example designs to utilize UDP checksum modules 2016-09-30 22:15:21 -07:00
Alex Forencich
5eb0d9f578 Move invert to top-level module 2016-01-25 13:21:35 -08:00
Alex Forencich
eb8dd775a1 Add 10G reference design for DE5-Net 2016-01-25 00:53:06 -08:00