FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-28 07:03:08 +08:00
Code Issues Projects Releases Wiki Activity
58 Commits 1 Branch 0 Tags
Commit Graph

2 Commits

Author SHA1 Message Date
Alex Forencich
b07c2d63b0 Parametrize tag and counter widths 2014-11-19 23:06:43 -08:00
Alex Forencich
7c3adb6c2b Add AXI stream frame joiner, generator, and testbench 2014-10-22 10:47:03 -07:00