FPGA/verilog-ethernet
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4 Commits

Author SHA1 Message Date
Alex Forencich
51b5335318 Remove z from default states for FSM inference 2015-03-09 02:38:39 -07:00
Alex Forencich
d483ebb8da Drop arp request earlier 2014-11-20 23:59:54 -08:00
Alex Forencich
fc6ccd97fb Rework IP modules 2014-11-20 12:11:11 -08:00
Alex Forencich
fc304ed1ba Add 64 bit IP module and testbench 2014-09-30 17:41:38 -07:00