FPGA/verilog-ethernet
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4 Commits

Author SHA1 Message Date
Alex Forencich
5415c41c41 Remove string parameters 2021-06-02 17:50:26 -07:00
Alex Forencich
839ea23ac4 Fix arb mux header backpressure 2020-05-17 21:50:24 -07:00
Alex Forencich
db56c938bf Replace generate with assign 2019-12-17 00:09:38 -08:00
Alex Forencich
96cefbe0c1 Convert generated eth_arb_mux to verilog parametrized module 2018-10-31 21:42:28 -07:00