FPGA/verilog-ethernet
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675 Commits 1 Branch 0 Tags
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15 Commits

Author SHA1 Message Date
Alex Forencich
1d3554c37e Rework pointer handling to improve timing 2019-06-16 23:53:26 -07:00
Alex Forencich
6b1b36ded6 Assert header ready earlier if possible 2018-11-07 23:10:07 -08:00
Alex Forencich
d2fedc4134 Rename ports 2018-11-07 22:35:06 -08:00
Alex Forencich
0fd157964a Happy new year 2018-02-26 12:50:51 -08:00
Alex Forencich
9b2ac9dfc1 Happy new year 2017-05-18 13:47:45 -07:00
Alex Forencich
9c01e114b4 Happy new year 2016-01-05 00:34:32 -08:00
Alex Forencich
a98dfce099 Update output registers, remove extraneous resets, fix constant widths 2015-11-09 23:50:34 -08:00
Alex Forencich
cc5fead04d Convert to synchronous resets 2015-10-09 22:36:58 -07:00
Alex Forencich
51b5335318 Remove z from default states for FSM inference 2015-03-09 02:38:39 -07:00
Alex Forencich
6b4dd02946 Resolve multiple driver issue 2015-02-28 00:43:27 -08:00
Alex Forencich
867b799ecd Rework IP datapath modules to separate output register 2014-10-28 01:00:52 -07:00
Alex Forencich
8191b38e7a Move header valid assign to top 2014-09-25 16:25:37 -07:00
Alex Forencich
5eaba1c3b3 Do not clock out a header if the last signal falls on the last word 2014-09-24 23:52:41 -07:00
Alex Forencich
119958cccb Remove unused parameter 2014-09-21 15:54:54 -07:00
Alex Forencich
4bee0542b7 Add IP modules (8 bit datapath) 2014-09-19 17:35:51 -07:00