FPGA/verilog-ethernet
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816 Commits 1 Branch 0 Tags
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5 Commits

Author SHA1 Message Date
Alex Forencich
0359d8d76a Use absolute path to test directory 2020-12-28 19:25:59 -08:00
Alex Forencich
079d6329cb Migrate example design testbenches to cocotb 2020-12-28 01:11:03 -08:00
Alex Forencich
bf9f1a6211 Update flash programming commands 2020-09-29 18:29:27 -07:00
Alex Forencich
3f52ed675c Fix flash settings 2020-09-29 17:30:13 -07:00
Alex Forencich
6254158e1b Add AU200 10G example design 2020-09-18 01:20:20 -07:00