FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-28 07:03:08 +08:00
Code Issues Projects Releases Wiki Activity
328 Commits 1 Branch 0 Tags
Commit Graph

4 Commits

Author SHA1 Message Date
Alex Forencich
e38ffe16b8 Adjust config vector assignment 2016-07-13 14:38:22 -04:00
Alex Forencich
018b3b2691 Fix signal width 2016-07-13 12:21:37 -04:00
Alex Forencich
61d41789d7 Remove unused parameter; update XDC file 2016-07-13 11:57:14 -04:00
Alex Forencich
5afe1d7e1e Add example design for VCU108 board 2016-07-05 11:52:28 -04:00