FPGA/verilog-ethernet
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4 Commits

Author SHA1 Message Date
Alex Forencich
9c01e114b4 Happy new year 2016-01-05 00:34:32 -08:00
Alex Forencich
a98dfce099 Update output registers, remove extraneous resets, fix constant widths 2015-11-09 23:50:34 -08:00
Alex Forencich
cc5fead04d Convert to synchronous resets 2015-10-09 22:36:58 -07:00
Alex Forencich
9bf6f01649 Add 2 port Ethernet mux components 2014-11-21 00:02:20 -08:00