FPGA/verilog-ethernet
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5 Commits

Author SHA1 Message Date
Alex Forencich
ca11618e6d Convert to synchronous resets 2015-10-08 11:26:32 -07:00
Alex Forencich
3d17cc1cee Adjust rate limiter framing logic 2015-05-12 17:58:09 -07:00
Alex Forencich
3816eb3c20 Fix parameters 2014-11-12 02:06:18 -08:00
Alex Forencich
5f14df216a Improve output register filling 2014-10-22 15:11:41 -07:00
Alex Forencich
377ef5accb Initial commit of AXI stream rate limiter 2014-10-20 15:09:07 -07:00