FPGA/verilog-ethernet
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3 Commits

Author SHA1 Message Date
Alex Forencich
82cf0d5a6f Use correct init_clk frequency 2020-09-23 14:24:18 -07:00
Alex Forencich
6a4bcaab38 Add timing constraints for LED driver 2020-09-22 22:13:59 -07:00
Alex Forencich
a7972e32bb Add fb2CG 10G example design 2020-09-20 01:18:47 -07:00