FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-14 06:43:18 +08:00
Code Issues Projects Releases Wiki Activity
746 Commits 1 Branch 0 Tags
Commit Graph

3 Commits

Author SHA1 Message Date
Alex Forencich
839ea23ac4 Fix arb mux header backpressure 2020-05-17 21:50:24 -07:00
Alex Forencich
db56c938bf Replace generate with assign 2019-12-17 00:09:38 -08:00
Alex Forencich
554e0a5380 Convert generated ip_arb_mux to verilog parametrized module 2018-11-01 00:40:09 -07:00