FPGA/verilog-ethernet
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3 Commits

Author SHA1 Message Date
Alex Forencich
88150c9d5f Update and rework endpoints, update testbenches 2016-09-13 15:24:02 -07:00
Alex Forencich
1f52bf826d Update vivado.mk 2016-07-05 11:17:16 -04:00
Alex Forencich
cbf1df718a Add example design for Digilent Nexys Video board 2016-06-29 12:00:05 -07:00