FPGA/verilog-ethernet
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4 Commits

Author SHA1 Message Date
Alex Forencich
885d847514 Rework header ready set 2014-11-17 19:27:45 -08:00
Alex Forencich
59952bd8cf Do not accept new frame until header is read 2014-11-17 18:10:35 -08:00
Alex Forencich
f1d075d974 Add enable signal 2014-11-16 02:13:43 -08:00
Alex Forencich
9bee01e74c Add ethernet mux and testbench 2014-11-14 17:48:51 -08:00