FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-28 07:03:08 +08:00
Code Issues Projects Releases Wiki Activity
1,063 Commits 1 Branch 0 Tags
Commit Graph

5 Commits

Author SHA1 Message Date
Alex Forencich
c65161e696 Remove recursively-expanded macros for module parameters in makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-17 16:04:16 -08:00
Alex Forencich
ab0c382123 Rework parameter handling in makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-29 21:03:16 -08:00
Alex Forencich
23fb9d0bd8 Remove deprecated assignments 2022-03-16 18:43:36 -07:00
Alex Forencich
1f80696b55 Use start_soon instead of fork 2021-12-10 18:19:11 -08:00
Alex Forencich
7117de682a Add cocotb testbench for ptp_perout 2020-12-29 22:02:27 -08:00