FPGA/verilog-ethernet
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2 Commits

Author SHA1 Message Date
Alex Forencich
c021d01c26 Update example design readmes 2021-05-04 15:48:12 -07:00
Alex Forencich
5a7fd98413 Add KC705 RGMII example design 2020-12-30 17:15:18 -08:00