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Author	SHA1	Message	Date
Alex Forencich	99b06b0ed2	Update readme	2020-09-22 23:04:44 -07:00
Alex Forencich	6a4bcaab38	Add timing constraints for LED driver	2020-09-22 22:13:59 -07:00
Alex Forencich	a7972e32bb	Add fb2CG 10G example design	2020-09-20 01:18:47 -07:00
Alex Forencich	c9d8b8508e	Update readme	2020-09-18 01:26:17 -07:00
Alex Forencich	4db7f50ad8	Update readme	2020-09-18 01:26:09 -07:00
Alex Forencich	c9a023c1e0	Add AU250 10G example design	2020-09-18 01:20:42 -07:00
Alex Forencich	6254158e1b	Add AU200 10G example design	2020-09-18 01:20:20 -07:00
Alex Forencich	b65bc94b4c	Update readme	2020-09-18 00:16:25 -07:00
Alex Forencich	9a8ba2f0f2	Add ZCU102 example design	2020-09-18 00:15:21 -07:00
Alex Forencich	6df648ef54	merged changes in axis	2020-09-07 18:55:12 -07:00
Alex Forencich	da152a8546	Update timing parameters for async FIFO to reflect new pipeline register naming	2020-09-07 18:54:32 -07:00
Alex Forencich	71b6b9f6f2	Prevent shift register inference	2020-09-07 18:54:18 -07:00
Alex Forencich	dff38e2c1d	Add UDP test script	2020-09-07 16:32:00 -07:00
Alex Forencich	ad47169480	Add netns shell script	2020-09-07 16:28:18 -07:00
Alex Forencich	591527f5a7	Pass through FIFO pipeline parameters	2020-09-07 13:26:34 -07:00
Alex Forencich	59a9585253	merged changes in axis	2020-09-07 00:42:44 -07:00
Alex Forencich	ede73b434a	Add PIPELINE_OUTPUT parameter to FIFO adapter modules	2020-09-07 00:22:55 -07:00
Alex Forencich	2f883681d6	Add pararametrizable output pipeline to FIFOs	2020-09-07 00:14:22 -07:00
Alex Forencich	eb6861cbc4	Convert to single always block	2020-09-06 22:57:56 -07:00
Alex Forencich	c9950d56ae	Rewrite full/empty logic	2020-09-06 18:28:32 -07:00
Alex Forencich	b7ed61b242	Rewrite resets	2020-09-06 17:55:10 -07:00
Alex Forencich	84cffeca5f	Remove unneeded address registers	2020-09-06 17:52:41 -07:00
Alex Forencich	4b5cdce7ab	merged changes in axis	2020-09-03 15:56:55 -07:00
Alex Forencich	a7689b6772	Pipeline RAM output in RAM switch	2020-09-03 15:55:45 -07:00
Alex Forencich	62d696a1dc	merged changes in axis	2020-08-17 18:31:56 -07:00
Alex Forencich	ae10935a93	Rewrite priority encoder to remove recusive construction	2020-08-17 18:29:05 -07:00
Alex Forencich	d97e95b6c7	Update XDC	2020-08-06 22:06:40 -07:00
Alex Forencich	2e3f2c97b6	Update readme	2020-08-06 18:26:18 -07:00
Alex Forencich	df5368d153	Add ZCU106 example design	2020-08-06 18:26:07 -07:00
Alex Forencich	6aba3a741a	Update makefiles	2020-08-06 17:19:11 -07:00
Alex Forencich	fd908dd2aa	Clean up clock connections	2020-08-06 17:15:38 -07:00
Alex Forencich	dbd6f0f07c	Update readme	2020-07-17 00:07:45 -07:00
Alex Forencich	f0e130aa48	Add AU50 10G example design	2020-07-17 00:06:32 -07:00
Alex Forencich	2570c75a0c	Clean up AU280 design	2020-07-16 23:55:12 -07:00
Alex Forencich	4fbf30c34c	Update readme	2020-07-15 00:07:06 -07:00
Alex Forencich	f2f3c0f977	Add AU280 10G example design	2020-07-15 00:06:38 -07:00
Alex Forencich	b7c089dd22	XDC clean up	2020-07-13 23:58:30 -07:00
Alex Forencich	ce41b4c5ea	Update readme	2020-07-10 16:07:31 -07:00
Alex Forencich	3898cf21ed	Add DE2-115 example design	2020-07-10 15:38:43 -07:00
Alex Forencich	3b06f86dcf	Add C10LP example design	2020-07-10 15:32:39 -07:00
Alex Forencich	59a51b4a9f	Add SDC constraints for Quartus	2020-07-10 14:14:02 -07:00
Alex Forencich	65cb3cb441	merged changes in axis	2020-07-10 14:04:52 -07:00
Alex Forencich	71bd4a1811	Add SDC constraints for Quartus	2020-07-10 14:02:08 -07:00
Alex Forencich	a27c04a949	Convert to TCL IP	2020-07-01 19:43:26 -07:00
Alex Forencich	839ea23ac4	Fix arb mux header backpressure	2020-05-17 21:50:24 -07:00
Alex Forencich	b31c390d3e	Assume tkeep[0] always high	2020-05-05 16:17:51 -07:00
Alex Forencich	4d4c7df5b6	Parametrize eth_axis_fcs	2020-05-05 16:13:02 -07:00
Alex Forencich	4754d94736	Fix backpressure bug	2020-04-17 21:22:07 -07:00
Alex Forencich	8d909a082f	Fix MAC FIFO parameters	2020-04-06 21:15:17 -07:00
Alex Forencich	73bd619d85	Add NetFPGA SUME example design	2020-03-27 19:01:50 -07:00