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Author SHA1 Message Date
Alex Forencich
27ed447005 Use common sync_reset module files 2020-03-27 18:27:45 -07:00
Alex Forencich
12083439ac merged changes in axis 2020-03-27 18:04:39 -07:00
Alex Forencich
fd1ec1690f Add sync_reset module and timing constraints 2020-03-27 18:04:04 -07:00
Alex Forencich
fd4a6db850 Update readme 2020-02-23 17:19:50 -08:00
Alex Forencich
1443c04ed3 Add missing reset 2020-02-23 17:18:59 -08:00
Alex Forencich
a55c354924 Parametrize Ethernet frame parsing 2020-02-21 21:37:57 -08:00
Alex Forencich
7994db90b1 Set initial tkeep state in testbenches 2020-02-21 15:18:21 -08:00
Alex Forencich
8618b24dea Force tkeep output high if KEEP_ENABLE is false 2020-02-21 14:30:13 -08:00
Alex Forencich
4ac6d6803b Parametrize ARP components 2020-02-20 16:49:47 -08:00
Alex Forencich
f9915b2f31 Refactor 2020-02-19 21:32:00 -08:00
Alex Forencich
406a3d69d1 Rework read handling 2020-02-19 21:24:15 -08:00
Alex Forencich
2876235a72 Throughput optimizations 2020-02-19 18:15:58 -08:00
Alex Forencich
b2e8e2d7a7 Update readme 2020-02-18 01:06:36 -08:00
Alex Forencich
52d1117753 Add AXI stream RAM switch module and testbenches 2020-02-18 01:06:14 -08:00
Alex Forencich
815705f413 Add VCU1525 10G example design 2020-01-15 23:14:08 -08:00
Alex Forencich
db56c938bf Replace generate with assign 2019-12-17 00:09:38 -08:00
Alex Forencich
b34f294900 Add ExaNIC X25 10G example design 2019-10-30 17:14:27 -07:00
Alex Forencich
9ef08c9d5d merged changes in axis 2019-10-24 12:09:16 -07:00
Alex Forencich
a9c04a4651 Fix frame FIFO drop 2019-10-24 12:08:08 -07:00
Alex Forencich
b3c654461e Update example design 2019-10-22 23:17:39 -07:00
Alex Forencich
e9c1c5a49d Fix state register width 2019-08-12 15:12:21 -07:00
Alex Forencich
6795c25e7f Fix use before define 2019-08-09 18:05:32 -07:00
Alex Forencich
e9949f57a9 Remove extraneous code 2019-08-05 13:27:12 -07:00
Alex Forencich
cdfa01e2aa Add checksum verification methods 2019-07-29 18:54:37 -07:00
Alex Forencich
bfef06ca0e Separate UDP pseudo header checksum computation 2019-07-29 18:53:32 -07:00
Alex Forencich
ce00df8de1 Include instance names in error messages 2019-07-25 16:30:10 -07:00
Alex Forencich
562e713837 Remove extraneous connections 2019-07-25 15:34:32 -07:00
Alex Forencich
0a85a4a2aa Fix assert 2019-07-25 00:43:42 -07:00
Alex Forencich
592ae7e6a2 Change default switch addressing to use MSBs of tdest 2019-07-25 00:40:13 -07:00
Alex Forencich
f32d7d0dec merged changes in axis 2019-07-24 15:39:00 -07:00
Alex Forencich
76c805e416 Fix more indexing bugs 2019-07-24 15:38:49 -07:00
Alex Forencich
8179a32b7d Pass all parameters in testbenches 2019-07-24 15:26:49 -07:00
Alex Forencich
1085d651a0 merged changes in axis 2019-07-24 15:23:00 -07:00
Alex Forencich
23b9490fac Fix switch bug 2019-07-24 15:22:35 -07:00
Alex Forencich
099bb0e8b5 merged changes in axis 2019-07-24 14:26:48 -07:00
Alex Forencich
5f454d6c05 Update axis_switch to support default routing configurations 2019-07-24 14:20:07 -07:00
Alex Forencich
c5f44c70d1 Add parameter documentation 2019-07-24 13:54:21 -07:00
Alex Forencich
c091f7ed76 Add switch wrapper generator 2019-07-24 13:46:33 -07:00
Alex Forencich
b4cebd8394 Fix crosspoint wrapper generator 2019-07-24 13:44:43 -07:00
Alex Forencich
c759ff03b7 Fix default parameter 2019-07-24 11:07:17 -07:00
Alex Forencich
ab77ac3858 Fix width 2019-07-19 18:16:07 -07:00
Alex Forencich
451db171d1 Don't leave output floating 2019-07-19 18:13:30 -07:00
Alex Forencich
c5e886769a Fix typo 2019-07-19 10:29:55 -07:00
Alex Forencich
16d1662d98 Add PTP timestamping infrastructure to 10G MACs 2019-07-18 23:13:46 -07:00
Alex Forencich
4e49dbcf3d Pass parameters to model 2019-07-18 22:51:54 -07:00
Alex Forencich
8cb0a5e06e Add parameters for PTP clock model 2019-07-18 22:49:29 -07:00
Alex Forencich
16755720d3 Add PTP tag inserter module 2019-07-18 22:39:50 -07:00
Alex Forencich
b26f923c2f Reset synchronizers 2019-07-18 18:35:30 -07:00
Alex Forencich
adb9c4d147 Fix initial values 2019-07-18 18:35:11 -07:00
Alex Forencich
16e5ec2106 Update example designs 2019-07-18 17:13:47 -07:00