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Author SHA1 Message Date
Alex Forencich
3bd7be44fa Update FIFO instances and update MACs to use combined FIFO adapter module 2019-07-18 16:25:49 -07:00
Alex Forencich
3a79b8fb17 merged changes in axis 2019-07-18 11:50:56 -07:00
Alex Forencich
8b2f37d5cc Update readme 2019-07-18 11:28:19 -07:00
Alex Forencich
69de6fd2a4 Convert FIFOs to use DEPTH parameter instead of ADDR_WIDTH 2019-07-18 11:27:25 -07:00
Alex Forencich
e0a1a73ce0 Mask tdata with tkeep 2019-07-18 11:01:00 -07:00
Alex Forencich
4da1a83052 Constant FIFO depth 2019-07-17 23:36:10 -07:00
Alex Forencich
021c91fcc7 Unconditionally wait at least one delta cycle 2019-07-16 00:37:20 -07:00
Alex Forencich
583849e0db merged changes in axis 2019-07-16 00:30:49 -07:00
Alex Forencich
1d5a4db0d5 Unconditionally wait at least one delta cycle 2019-07-16 00:30:19 -07:00
Alex Forencich
1279dcbf47 Back out previous change 2019-07-15 18:09:14 -07:00
Alex Forencich
cc1ff34f53 Add 64 bit timestamp support to ptp_clock_cdc 2019-07-15 16:36:02 -07:00
Alex Forencich
31cb54e67e Make old icarus verilog happy 2019-07-15 16:15:50 -07:00
Alex Forencich
ef3a39e933 Update readme 2019-07-15 15:31:25 -07:00
Alex Forencich
c719b57474 Update readme 2019-07-15 15:27:46 -07:00
Alex Forencich
9d553f2ad4 Also need to use tready 2019-07-15 15:24:12 -07:00
Alex Forencich
d88ada105d Add PTP TS extract module 2019-07-15 15:17:58 -07:00
Alex Forencich
77bae7a77e Add PTP clock CDC module and testbench 2019-07-15 15:16:17 -07:00
Alex Forencich
e5171d8749 Enable flash programming in VCU118 example designs 2019-07-01 17:51:31 -07:00
Alex Forencich
fdfb517761 Add PTP perout module and testbench 2019-06-27 01:30:18 -07:00
Alex Forencich
386ff91210 Add ExaNIC X10 flash programming commands 2019-06-27 01:27:32 -07:00
Alex Forencich
d62a5ad050 Fix quotes 2019-06-27 01:26:58 -07:00
Alex Forencich
dfafa9c83d Update vivado.mk 2019-06-27 00:59:36 -07:00
Alex Forencich
025f05e667 Add nojournal and nolog 2019-06-27 00:48:20 -07:00
Alex Forencich
af4f675840 Fix for dash 2019-06-27 00:15:36 -07:00
Alex Forencich
cfcd9da375 Update IP 2019-06-26 20:50:05 -07:00
Alex Forencich
15b3aaf2e7 Update programming commands 2019-06-26 20:17:45 -07:00
Alex Forencich
963a8f7459 Add flash ADM-PCIE-9V3 flash programming commands 2019-06-26 20:06:22 -07:00
Alex Forencich
88cc4e6e24 Update VCU108 flash programming commands 2019-06-26 19:50:28 -07:00
Alex Forencich
dc4416a261 Update Arty flash programming commands 2019-06-26 19:00:20 -07:00
Alex Forencich
d166350d77 Update Arty XDC 2019-06-26 18:59:41 -07:00
Alex Forencich
daf1d3106f Enable flash programming on VCU108 2019-06-26 01:28:54 -07:00
Alex Forencich
7cce7896b5 Update programming commands 2019-06-25 23:46:44 -07:00
Alex Forencich
df04d7e68d CRC handling logic optimizations 2019-06-20 18:10:53 -07:00
Alex Forencich
9e7f4a9836 Remove unused state bit 2019-06-20 18:02:15 -07:00
Alex Forencich
0927f4c326 Fix readme 2019-06-19 23:51:04 -07:00
Alex Forencich
4410d74848 Update readme 2019-06-19 23:28:15 -07:00
Alex Forencich
1eb9c39ed3 Add VCU118 25G example design 2019-06-19 23:25:06 -07:00
Alex Forencich
1a28b0bf67 Add ADM-PCIE-9V3 25G example design 2019-06-19 23:22:56 -07:00
Alex Forencich
a031993b26 Update example designs 2019-06-19 23:16:57 -07:00
Alex Forencich
eb1f38a749 More critical path optimizations 2019-06-19 15:06:55 -07:00
Alex Forencich
134ce04777 Add configurable serdes pipeline register chain 2019-06-19 00:57:28 -07:00
Alex Forencich
3ba91ce091 Wait for block lock 2019-06-19 00:53:41 -07:00
Alex Forencich
303dec8165 Sum errors across data and header 2019-06-19 00:25:41 -07:00
Alex Forencich
1d3554c37e Rework pointer handling to improve timing 2019-06-16 23:53:26 -07:00
Alex Forencich
7ec836baf6 IP header checksum optimizations 2019-06-16 22:01:11 -07:00
Alex Forencich
b17966f73d store_last_word timing optimization 2019-06-16 20:01:08 -07:00
Alex Forencich
55bf44117b shift_axis_extra_cycle timing optimization 2019-06-16 19:57:52 -07:00
Alex Forencich
3b959b2765 CRC handling logic optimizations 2019-06-16 17:39:28 -07:00
Alex Forencich
320a45c4ab Remove unused state bit 2019-06-16 17:33:14 -07:00
Alex Forencich
8bb243cd35 MAC termination detect timing optimizations 2019-06-16 15:44:41 -07:00