FPGA/verilog-ethernet
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11 Commits

Author SHA1 Message Date
Alex Forencich
9b2ac9dfc1 Happy new year 2017-05-18 13:47:45 -07:00
Alex Forencich
9c01e114b4 Happy new year 2016-01-05 00:34:32 -08:00
Alex Forencich
a98dfce099 Update output registers, remove extraneous resets, fix constant widths 2015-11-09 23:50:34 -08:00
Alex Forencich
cc5fead04d Convert to synchronous resets 2015-10-09 22:36:58 -07:00
Alex Forencich
51b5335318 Remove z from default states for FSM inference 2015-03-09 02:38:39 -07:00
Alex Forencich
0e26b3a8a4 Put back lane shifting logic 2014-10-28 00:54:15 -07:00
Alex Forencich
205be7ed27 Rework AXI ethernet modules to separate output register 2014-10-23 00:05:06 -07:00
Alex Forencich
d7f30a777b Update comments 2014-09-15 19:05:18 -07:00
Alex Forencich
a8958f4b23 Remove unnecessary registers 2014-09-15 19:04:49 -07:00
Alex Forencich
46c29160ff Wait for header instead of payload 2014-09-15 19:03:31 -07:00
Alex Forencich
8e4d162667 Add ethernet frame to AXI stream modules 2014-09-14 01:06:48 -07:00