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Author	SHA1	Message	Date
Alex Forencich	9cca78bc7c	Fix last cycle detect logic	2015-04-19 23:33:34 -07:00
Alex Forencich	7795a9182b	Remove tristate for state machine inference	2015-04-19 23:08:41 -07:00
Alex Forencich	966e47a826	Fix RAM and register widths	2015-04-19 23:06:30 -07:00
Alex Forencich	9b7bad92f2	Reset pointers correctly	2015-04-19 17:51:27 -07:00
Alex Forencich	8cd0d3ee06	Update .travis.yml	2015-03-21 04:49:43 -07:00
Alex Forencich	eb9f7c13f1	Update .travis.yml	2015-03-21 04:47:21 -07:00
Alex Forencich	684f6967e5	Update .travis.yml	2015-03-21 04:40:57 -07:00
Alex Forencich	646ad2a293	Update .travis.yml	2015-03-21 04:39:27 -07:00
Alex Forencich	6bd28aa128	Update .travis.yml	2015-03-21 04:36:54 -07:00
Alex Forencich	d9c41d43f0	Update .travis.yml	2015-03-21 04:28:53 -07:00
Alex Forencich	d00471352f	Update .travis.yml	2015-03-21 04:24:52 -07:00
Alex Forencich	7b991bfe0e	Update AXI stream endpoint to support multiple tdata signals	2015-03-21 03:35:42 -07:00
Alex Forencich	30e597e3e0	Test with python 3	2015-03-21 03:32:42 -07:00
Alex Forencich	02a7f4d5ed	Update testbenches to python 3	2015-03-21 03:32:19 -07:00
Alex Forencich	54bfdaa8c0	Cast WL to int	2015-03-21 03:19:43 -07:00
Alex Forencich	4981d7cacd	Update MyHDL repo	2015-03-21 02:56:17 -07:00
Alex Forencich	3138795899	Fix rate limiter testbenches	2015-03-21 02:55:30 -07:00
Alex Forencich	6e2eda256d	Improve frame drop logic in frame FIFOs, add DROP_WHEN_FULL option to disable input tready signal	2015-02-28 19:32:08 -08:00
Alex Forencich	8582ab0749	Update readme	2014-12-03 19:00:12 -08:00
Alex Forencich	3c7e3b0424	Add SRL register module and testbench	2014-12-03 18:51:46 -08:00
Alex Forencich	10fd51f192	Add SRL FIFO module and testbench	2014-12-03 18:49:33 -08:00
Alex Forencich	385e358c08	Use non-broken myhdl	2014-12-03 18:02:53 -08:00
Alex Forencich	b83dd34185	Fix register names	2014-12-03 13:15:13 -08:00
Alex Forencich	fbcbbe3a69	Remove adder tree	2014-11-21 10:43:20 -08:00
Alex Forencich	63f6e96492	Add tuser signal to crosspoint module	2014-11-21 01:07:02 -08:00
Alex Forencich	27cb9609f1	clog2 does not work in localparam in XST	2014-11-21 01:06:24 -08:00
Alex Forencich	b07c2d63b0	Parametrize tag and counter widths	2014-11-19 23:06:43 -08:00
Alex Forencich	0c3af7d5bb	Reverse priority in arbitrated mux	2014-11-16 02:00:27 -08:00
Alex Forencich	d193ca5905	Add LSB_PRIORITY parameter	2014-11-16 01:58:17 -08:00
Alex Forencich	b123525597	Add enable signal	2014-11-16 01:38:20 -08:00
Alex Forencich	7c86999399	Minor reorganization	2014-11-13 16:26:07 -08:00
Alex Forencich	789c7da6d6	Fix parameter	2014-11-13 10:39:41 -08:00
Alex Forencich	698234c297	Update comments	2014-11-13 10:39:27 -08:00
Alex Forencich	8a46e6900c	Update readme	2014-11-13 10:21:54 -08:00
Alex Forencich	bd90208153	Update readme	2014-11-13 10:19:46 -08:00
Alex Forencich	851aeb9309	Fix block parameter	2014-11-13 10:06:28 -08:00
Alex Forencich	5f0d23a3ad	Add AXI arbitrated mux module and testbench	2014-11-13 02:01:45 -08:00
Alex Forencich	a8970e6e75	Change block parameter	2014-11-13 02:01:07 -08:00
Alex Forencich	a1633f27d8	Add arbiter module	2014-11-13 01:22:59 -08:00
Alex Forencich	3399f284b2	Add priority encoder	2014-11-12 23:59:02 -08:00
Alex Forencich	5c49ed6191	Add AXI stream demux and testbench	2014-11-12 19:21:28 -08:00
Alex Forencich	73a580df95	Update readme	2014-11-12 15:53:47 -08:00
Alex Forencich	5af6dc3501	Add AXI stream mux and testbench	2014-11-12 15:49:07 -08:00
Alex Forencich	aafacb372e	Trim trailing spaces	2014-11-12 15:32:05 -08:00
Alex Forencich	3816eb3c20	Fix parameters	2014-11-12 02:06:18 -08:00
Alex Forencich	d6784d189d	Update readme	2014-11-12 02:03:59 -08:00
Alex Forencich	a28a534bff	Add AXI stream crosspoint module and testbench	2014-11-12 01:54:31 -08:00
Alex Forencich	7804272b2e	Updated readme	2014-11-09 02:13:20 -08:00
Alex Forencich	10e0d7d1bb	Add AXI async frame fifo and testbench	2014-11-08 21:29:39 -08:00
Alex Forencich	6fa46b6c57	Add AXI frame fifo and testbench	2014-11-08 21:07:47 -08:00