FPGA/verilog-ethernet
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7 Commits

Author SHA1 Message Date
Alex Forencich
b3f50ac2c7 Fix comments 2018-11-02 00:40:15 -07:00
Alex Forencich
67025121ab Convert generated udp_mux to verilog parametrized module 2018-10-31 18:09:44 -07:00
Alex Forencich
0fd157964a Happy new year 2018-02-26 12:50:51 -08:00
Alex Forencich
9b2ac9dfc1 Happy new year 2017-05-18 13:47:45 -07:00
Alex Forencich
88150c9d5f Update and rework endpoints, update testbenches 2016-09-13 15:24:02 -07:00
Alex Forencich
9c01e114b4 Happy new year 2016-01-05 00:34:32 -08:00
Alex Forencich
a5d68fcff9 Add UDP mux module and testbench 2014-11-18 14:41:48 -08:00