FPGA/verilog-ethernet
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10 Commits

Author SHA1 Message Date
Alex Forencich
0fd157964a Happy new year 2018-02-26 12:50:51 -08:00
Alex Forencich
bb9e789645 Update GMII PHY interface and add GMII MAC wrappers 2017-05-31 18:40:18 -07:00
Alex Forencich
9b2ac9dfc1 Happy new year 2017-05-18 13:47:45 -07:00
Alex Forencich
15330486e8 Convert GMII and RGMII shims to use generic IO components 2016-09-29 20:10:10 -07:00
Alex Forencich
b38c643384 Add more implementation parameters to gmii_phy_if 2016-06-28 19:35:52 -07:00
Alex Forencich
152486bebd Update parametrization 2016-01-08 01:30:00 -08:00
Alex Forencich
9c01e114b4 Happy new year 2016-01-05 00:34:32 -08:00
Alex Forencich
a98dfce099 Update output registers, remove extraneous resets, fix constant widths 2015-11-09 23:50:34 -08:00
Alex Forencich
d57c857d88 Put PHY interface registers into IOBs for timing 2015-02-28 18:24:20 -08:00
Alex Forencich
7532915bb7 Add GMII PHY interface module 2015-02-28 01:11:03 -08:00