FPGA/verilog-ethernet
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11 Commits

Author SHA1 Message Date
Alex Forencich
d2fedc4134 Rename ports 2018-11-07 22:35:06 -08:00
Alex Forencich
5b7646ccda Rework ARP subsystem 2018-06-18 13:59:58 -07:00
Alex Forencich
0fd157964a Happy new year 2018-02-26 12:50:51 -08:00
Alex Forencich
9b2ac9dfc1 Happy new year 2017-05-18 13:47:45 -07:00
Alex Forencich
9c01e114b4 Happy new year 2016-01-05 00:34:32 -08:00
Alex Forencich
a98dfce099 Update output registers, remove extraneous resets, fix constant widths 2015-11-09 23:50:34 -08:00
Alex Forencich
cc5fead04d Convert to synchronous resets 2015-10-09 22:36:58 -07:00
Alex Forencich
51b5335318 Remove z from default states for FSM inference 2015-03-09 02:38:39 -07:00
Alex Forencich
d483ebb8da Drop arp request earlier 2014-11-20 23:59:54 -08:00
Alex Forencich
fc6ccd97fb Rework IP modules 2014-11-20 12:11:11 -08:00
Alex Forencich
fc304ed1ba Add 64 bit IP module and testbench 2014-09-30 17:41:38 -07:00