FPGA/verilog-ethernet
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12 Commits

Author SHA1 Message Date
Alex Forencich
a031993b26 Update example designs 2019-06-19 23:16:57 -07:00
Alex Forencich
0ca8c9a59b Update example design timing constraints 2019-03-28 17:59:30 -07:00
Alex Forencich
d16d291d5e Upgrade example design IP cores 2019-03-28 16:30:34 -07:00
Alex Forencich
cd6b87e984 Enable bitstream compression in example designs 2019-02-06 21:25:30 -08:00
Alex Forencich
0a6bee6d69 Update example designs 2018-11-08 09:17:29 -08:00
Alex Forencich
7d6889add6 Update example designs 2018-10-30 21:32:32 -07:00
Alex Forencich
8982b4f4e1 Fix modsell pin 2018-06-29 13:00:41 -07:00
Alex Forencich
6368529b6f Add clock frequency annotation 2018-06-14 13:42:10 -07:00
Alex Forencich
e4672915e6 Update testbenches to use instances() 2018-06-13 22:43:11 -07:00
Alex Forencich
298ae4defa Update MAC module instantiation 2018-06-13 22:16:02 -07:00
Alex Forencich
05c6743473 Update xdc 2018-06-13 19:18:59 -07:00
Alex Forencich
f4d7edf23f Add VCU118 example design 2018-06-13 14:33:07 -07:00