FPGA/verilog-ethernet
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326 Commits 1 Branch 0 Tags
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7 Commits

Author SHA1 Message Date
Alex Forencich
073d50d9dc Round up default KEEP_WIDTH settings when DATA_WIDTH is not a multiple of 8 2022-03-30 16:02:17 -07:00
Alex Forencich
4df34f1344 Use start_soon instead of fork 2021-12-10 18:16:38 -08:00
Alex Forencich
2a89fb9332 Testbench parameter cleanup 2021-11-29 01:01:45 -08:00
Alex Forencich
907081d255 Add support to demux for routing by tdest 2021-11-28 23:09:10 -08:00
Alex Forencich
24863398c5 Decouple tid/tdest signal widths for routing components 2021-11-25 01:18:51 -08:00
Alex Forencich
f40e68350c Remove deprecated assigments 2021-11-15 14:39:47 -08:00
Alex Forencich
74c1014671 Add cocotb testbenches 2021-04-03 16:53:08 -07:00