FPGA/verilog-ethernet
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354 Commits 1 Branch 0 Tags
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13 Commits

Author SHA1 Message Date
Alex Forencich
b9e0af3634 Revert change to early ready conditions for improved throughput 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-18 12:07:11 -07:00
Alex Forencich
6d4458e5cc Rewrite early ready condition 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 17:36:00 -07:00
Alex Forencich
268d0c66b8 Rewrite resets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-13 12:57:41 -07:00
Alex Forencich
073d50d9dc Round up default KEEP_WIDTH settings when DATA_WIDTH is not a multiple of 8 2022-03-30 16:02:17 -07:00
Alex Forencich
e4b4762474 Handle some zero-valued signal width settings 2021-11-29 00:33:38 -08:00
Alex Forencich
907081d255 Add support to demux for routing by tdest 2021-11-28 23:09:10 -08:00
Alex Forencich
24863398c5 Decouple tid/tdest signal widths for routing components 2021-11-25 01:18:51 -08:00
Alex Forencich
150d5ad04e Handle out-of-range select as drop 2021-11-24 14:58:16 -08:00
Alex Forencich
2972a1fa81 Add default_nettype none and resetall directives 2021-10-20 15:33:38 -07:00
Alex Forencich
c5f44c70d1 Add parameter documentation 2019-07-24 13:54:21 -07:00
Alex Forencich
b1f3a74b86 Remove unused code 2019-03-07 22:59:15 -08:00
Alex Forencich
cadd1bcb50 Match width 2018-12-09 00:04:30 -08:00
Alex Forencich
9d813226d0 Convert generated demux to verilog parametrized demux 2018-10-24 22:16:05 -07:00