FPGA/verilog-ethernet
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133 Commits 1 Branch 0 Tags
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11 Commits

Author SHA1 Message Date
Alex Forencich
aebe0549dd Happy new year 2017-05-18 13:35:11 -07:00
Alex Forencich
0691c9d61b Fix output pipeline issue 2016-09-02 10:43:21 -07:00
Alex Forencich
a961a9756a Add FIFO output pipeline registers to aid block RAM output timing closure 2016-08-04 18:03:00 -07:00
Alex Forencich
6fe4a033e5 Add dedicated pipeline registers for RAM addresses that are not reset 2016-06-27 12:25:18 -07:00
Alex Forencich
385c9cc90a Fix Vivado block RAM inference 2016-06-27 12:10:36 -07:00
Alex Forencich
be4034071b Happy new year 2016-01-05 00:24:20 -08:00
Alex Forencich
0f0ebfb87d Reorganize FIFO modules 2015-11-07 01:15:11 -08:00
Alex Forencich
ca11618e6d Convert to synchronous resets 2015-10-08 11:26:32 -07:00
Alex Forencich
f387e4c300 Remove unused register 2015-07-09 11:13:12 -07:00
Alex Forencich
b232a6459d Remove counter from AXI fifo modules 2014-11-08 12:45:36 -08:00
Alex Forencich
35f39a6f4b Add AXI stream FIFO 2014-09-13 21:21:39 -07:00