FPGA/verilog-ethernet
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10 Commits

Author SHA1 Message Date
Alex Forencich
a5934dae60 Add PTP timestamping tests to MACs and related modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 23:21:42 -07:00
Alex Forencich
23fb9d0bd8 Remove deprecated assignments 2022-03-16 18:43:36 -07:00
Alex Forencich
1f80696b55 Use start_soon instead of fork 2021-12-10 18:19:11 -08:00
Alex Forencich
c44e447db5 Transfer PTP information in tuser 2021-09-01 15:56:00 -07:00
Alex Forencich
77938fa422 Update MAC modules for changes in FIFO modules 2021-08-26 00:55:12 -07:00
Alex Forencich
31c7349f90 Rewrite PTP clock CDC module for improved performance and timing closure at 25G 2021-03-30 15:57:46 -07:00
Alex Forencich
4af058fbdc Update testbenches 2021-03-06 20:04:19 -08:00
Alex Forencich
22b3bacf51 Update attribute name 2021-03-05 23:03:41 -08:00
Alex Forencich
77d22bfde0 Rework sim_build output directory, fix default makefile target 2020-12-29 14:47:12 -08:00
Alex Forencich
29dc7498d3 Add cocotb MAC testbenches 2020-12-28 19:26:46 -08:00