FPGA/verilog-ethernet
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5 Commits

Author SHA1 Message Date
Alex Forencich
4fa3870dea Remove string parameters 2021-06-02 15:08:43 -07:00
Alex Forencich
8e5c4874eb Fix switch wrapper parameters 2021-05-30 12:10:04 -07:00
Alex Forencich
9d99ec0096 Update wrapper generators 2021-04-03 16:34:42 -07:00
Alex Forencich
c5f44c70d1 Add parameter documentation 2019-07-24 13:54:21 -07:00
Alex Forencich
c091f7ed76 Add switch wrapper generator 2019-07-24 13:46:33 -07:00