FPGA/verilog-ethernet
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2 Commits

Author SHA1 Message Date
Alex Forencich
d2fedc4134 Rename ports 2018-11-07 22:35:06 -08:00
Alex Forencich
de69975872 Add AXI stream XGMII RX and TX modules and testbenches 2018-10-23 23:34:43 -07:00