FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-02-04 07:13:13 +08:00
Code Issues Projects Releases Wiki Activity
805 Commits 1 Branch 0 Tags
Commit Graph

2 Commits

Author SHA1 Message Date
Alex Forencich
d97e95b6c7 Update XDC 2020-08-06 22:06:40 -07:00
Alex Forencich
df5368d153 Add ZCU106 example design 2020-08-06 18:26:07 -07:00