FPGA/verilog-ethernet
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14 Commits 1 Branch 0 Tags
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11 Commits

Author SHA1 Message Date
Alex Forencich
a92eb4e57f Improve output register filling 2014-10-22 15:09:48 -07:00
Alex Forencich
7c3adb6c2b Add AXI stream frame joiner, generator, and testbench 2014-10-22 10:47:03 -07:00
Alex Forencich
67bb09ba42 Add busy output to statistics collection module 2014-10-21 16:09:55 -07:00
Alex Forencich
f22381baa2 Initial commit of basic statistics collection module 2014-10-21 13:20:37 -07:00
Alex Forencich
377ef5accb Initial commit of AXI stream rate limiter 2014-10-20 15:09:07 -07:00
Alex Forencich
e0c2f44dc2 Initial commit of AXI stream width adapter 2014-10-20 15:04:36 -07:00
Alex Forencich
2ec83046f6 Rework AXI stream register 2014-10-20 15:02:54 -07:00
Alex Forencich
ca50423036 Change default data width 2014-09-30 17:51:24 -07:00
Alex Forencich
e1955a29da Add LocalLink to AXI stream bridge 2014-09-13 21:23:11 -07:00
Alex Forencich
74fa967071 Add AXI stream register 2014-09-13 21:22:06 -07:00
Alex Forencich
35f39a6f4b Add AXI stream FIFO 2014-09-13 21:21:39 -07:00