FPGA/verilog-ethernet
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3 Commits

Author SHA1 Message Date
Alex Forencich
a98dfce099 Update output registers, remove extraneous resets, fix constant widths 2015-11-09 23:50:34 -08:00
Alex Forencich
cc5fead04d Convert to synchronous resets 2015-10-09 22:36:58 -07:00
Alex Forencich
a5d68fcff9 Add UDP mux module and testbench 2014-11-18 14:41:48 -08:00