FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-14 06:43:18 +08:00
Code Issues Projects Releases Wiki Activity
693 Commits 1 Branch 0 Tags
Commit Graph

100 Commits

Author SHA1 Message Date
Alex Forencich
16e5ec2106 Update example designs 2019-07-18 17:13:47 -07:00
Alex Forencich
e5171d8749 Enable flash programming in VCU118 example designs 2019-07-01 17:51:31 -07:00
Alex Forencich
386ff91210 Add ExaNIC X10 flash programming commands 2019-06-27 01:27:32 -07:00
Alex Forencich
d62a5ad050 Fix quotes 2019-06-27 01:26:58 -07:00
Alex Forencich
dfafa9c83d Update vivado.mk 2019-06-27 00:59:36 -07:00
Alex Forencich
025f05e667 Add nojournal and nolog 2019-06-27 00:48:20 -07:00
Alex Forencich
af4f675840 Fix for dash 2019-06-27 00:15:36 -07:00
Alex Forencich
cfcd9da375 Update IP 2019-06-26 20:50:05 -07:00
Alex Forencich
15b3aaf2e7 Update programming commands 2019-06-26 20:17:45 -07:00
Alex Forencich
963a8f7459 Add flash ADM-PCIE-9V3 flash programming commands 2019-06-26 20:06:22 -07:00
Alex Forencich
88cc4e6e24 Update VCU108 flash programming commands 2019-06-26 19:50:28 -07:00
Alex Forencich
dc4416a261 Update Arty flash programming commands 2019-06-26 19:00:20 -07:00
Alex Forencich
d166350d77 Update Arty XDC 2019-06-26 18:59:41 -07:00
Alex Forencich
daf1d3106f Enable flash programming on VCU108 2019-06-26 01:28:54 -07:00
Alex Forencich
7cce7896b5 Update programming commands 2019-06-25 23:46:44 -07:00
Alex Forencich
0927f4c326 Fix readme 2019-06-19 23:51:04 -07:00
Alex Forencich
1eb9c39ed3 Add VCU118 25G example design 2019-06-19 23:25:06 -07:00
Alex Forencich
1a28b0bf67 Add ADM-PCIE-9V3 25G example design 2019-06-19 23:22:56 -07:00
Alex Forencich
a031993b26 Update example designs 2019-06-19 23:16:57 -07:00
Alex Forencich
27999924a0 Update VCU108 example designs 2019-06-15 17:35:49 -07:00
Alex Forencich
352f52e159 Add flash target to Arty example design 2019-05-27 01:02:55 -07:00
Alex Forencich
249f9d9df4 Update example designs 2019-05-10 22:55:44 -07:00
Alex Forencich
2abb413854 Fix signal name 2019-05-02 20:30:37 -07:00
Alex Forencich
1d61626785 Add KC705 GMII example design 2019-05-02 19:29:47 -07:00
Alex Forencich
978fdce95c Minor fixes 2019-04-03 20:57:10 -07:00
Alex Forencich
5428d81fd6 Update AXI stream switch instances 2019-03-28 23:56:06 -07:00
Alex Forencich
0008956828 Add Arty example design 2019-03-28 19:38:55 -07:00
Alex Forencich
0ca8c9a59b Update example design timing constraints 2019-03-28 17:59:30 -07:00
Alex Forencich
e120a85607 Use correct clock 2019-03-28 17:56:55 -07:00
Alex Forencich
d16d291d5e Upgrade example design IP cores 2019-03-28 16:30:34 -07:00
Alex Forencich
cd6b87e984 Enable bitstream compression in example designs 2019-02-06 21:25:30 -08:00
Alex Forencich
52058cb5de Swap out PHY in VCU118 example design 2019-02-05 18:28:42 -08:00
Alex Forencich
5f6e7f721c Update testbench 2019-01-31 18:12:07 -08:00
Alex Forencich
07b4efa9ba Switch out Xilinx PHY core in ExaNIC X10 example design 2019-01-18 13:49:46 -08:00
Alex Forencich
0bbe062c66 Switch out Xilinx PHY core in ADM-PCIE-9V3 example design 2019-01-18 13:32:58 -08:00
Alex Forencich
2e29aea857 Fix input clock period settings 2019-01-17 19:09:47 -08:00
Alex Forencich
b8b504682a Fix transceiver clocking 2019-01-15 00:30:36 -08:00
Alex Forencich
6d52a7c0e7 Remove unneeded links 2019-01-08 17:31:49 -08:00
Alex Forencich
2628249059 Add ADM-PCIE-9V3 example design 2019-01-08 17:27:21 -08:00
Alex Forencich
1f793fa7d0 Update readme 2019-01-08 17:24:22 -08:00
Alex Forencich
82454e4ae1 Add ExaNIC X10 example design 2019-01-08 17:22:01 -08:00
Alex Forencich
e882ed143f Update example designs 2018-11-08 09:20:33 -08:00
Alex Forencich
0a6bee6d69 Update example designs 2018-11-08 09:17:29 -08:00
Alex Forencich
7d6889add6 Update example designs 2018-10-30 21:32:32 -07:00
Alex Forencich
00dc50826d Update example designs 2018-10-24 01:03:44 -07:00
Alex Forencich
030fe90bf5 Fix example design testbench 2018-10-19 15:33:25 -07:00
Alex Forencich
8982b4f4e1 Fix modsell pin 2018-06-29 13:00:41 -07:00
Alex Forencich
cd51821bf7 Add parameters 2018-06-22 18:56:05 -07:00
Alex Forencich
6368529b6f Add clock frequency annotation 2018-06-14 13:42:10 -07:00
Alex Forencich
e4672915e6 Update testbenches to use instances() 2018-06-13 22:43:11 -07:00