FPGA/verilog-ethernet
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693 Commits 1 Branch 0 Tags
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7 Commits

Author SHA1 Message Date
Alex Forencich
16e5ec2106 Update example designs 2019-07-18 17:13:47 -07:00
Alex Forencich
e5171d8749 Enable flash programming in VCU118 example designs 2019-07-01 17:51:31 -07:00
Alex Forencich
dfafa9c83d Update vivado.mk 2019-06-27 00:59:36 -07:00
Alex Forencich
025f05e667 Add nojournal and nolog 2019-06-27 00:48:20 -07:00
Alex Forencich
7cce7896b5 Update programming commands 2019-06-25 23:46:44 -07:00
Alex Forencich
0927f4c326 Fix readme 2019-06-19 23:51:04 -07:00
Alex Forencich
1eb9c39ed3 Add VCU118 25G example design 2019-06-19 23:25:06 -07:00