FPGA/verilog-ethernet
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3 Commits

Author SHA1 Message Date
Alex Forencich
77bae7a77e Add PTP clock CDC module and testbench 2019-07-15 15:16:17 -07:00
Alex Forencich
8e2d936884 Add MII PHY interface, MAC wrappers, and testbenches 2019-03-28 19:18:03 -07:00
Alex Forencich
58201866f3 Add timing constraints 2019-03-28 17:53:51 -07:00