FPGA/verilog-ethernet
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124 Commits 1 Branch 0 Tags
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8 Commits

Author SHA1 Message Date
Alex Forencich
aebe0549dd Happy new year 2017-05-18 13:35:11 -07:00
Alex Forencich
be4034071b Happy new year 2016-01-05 00:24:20 -08:00
Alex Forencich
0d22a35bd8 Update output registers, remove extraneous resets, fix constant widths 2015-11-08 23:05:38 -08:00
Alex Forencich
ca11618e6d Convert to synchronous resets 2015-10-08 11:26:32 -07:00
Alex Forencich
3d17cc1cee Adjust rate limiter framing logic 2015-05-12 17:58:09 -07:00
Alex Forencich
3816eb3c20 Fix parameters 2014-11-12 02:06:18 -08:00
Alex Forencich
5f14df216a Improve output register filling 2014-10-22 15:11:41 -07:00
Alex Forencich
377ef5accb Initial commit of AXI stream rate limiter 2014-10-20 15:09:07 -07:00