FPGA/verilog-ethernet
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8 Commits

Author SHA1 Message Date
Alex Forencich
aebe0549dd Happy new year 2017-05-18 13:35:11 -07:00
Alex Forencich
5fa36eeaa7 Rework endpoints, update testbenches 2016-09-12 13:38:34 -07:00
Alex Forencich
be4034071b Happy new year 2016-01-05 00:24:20 -08:00
Alex Forencich
364b537312 Synchronize status signals for both clock domains in async frame FIFO 2015-10-09 15:14:54 -07:00
Alex Forencich
30a35c3d73 Convert async fifo to common reset 2015-10-08 12:52:51 -07:00
Alex Forencich
e65173b7ee Add overflow, bad_frame, and good_frame status outputs to frame FIFOs 2015-05-12 17:52:41 -07:00
Alex Forencich
6e2eda256d Improve frame drop logic in frame FIFOs, add DROP_WHEN_FULL option to disable input tready signal 2015-02-28 19:32:08 -08:00
Alex Forencich
10e0d7d1bb Add AXI async frame fifo and testbench 2014-11-08 21:29:39 -08:00