FPGA/verilog-ethernet
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4 Commits

Author SHA1 Message Date
Alex Forencich
51b5335318 Remove z from default states for FSM inference 2015-03-09 02:38:39 -07:00
Alex Forencich
6b4dd02946 Resolve multiple driver issue 2015-02-28 00:43:27 -08:00
Alex Forencich
4474181549 Rework UDP datapath modules to separate output register 2014-10-28 01:55:29 -07:00
Alex Forencich
1acf493e9d Add 64 bit UDP transmit and receive modules 2014-09-25 17:28:05 -07:00