FPGA/verilog-ethernet
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12 Commits

Author SHA1 Message Date
Alex Forencich
9b2ac9dfc1 Happy new year 2017-05-18 13:47:45 -07:00
Alex Forencich
47ca9a8725 Replace eth_crc modules for generic lfsr module 2016-06-28 17:31:58 -07:00
Alex Forencich
9c01e114b4 Happy new year 2016-01-05 00:34:32 -08:00
Alex Forencich
a98dfce099 Update output registers, remove extraneous resets, fix constant widths 2015-11-09 23:50:34 -08:00
Alex Forencich
26aacea6ef Remove unused code 2015-10-28 12:40:23 -07:00
Alex Forencich
73e0a1cff4 Fail outgoing frames on tvalid deassert 2015-10-20 16:05:23 -07:00
Alex Forencich
475f897a31 Unconditional increment length 2015-10-20 16:04:47 -07:00
Alex Forencich
cc5fead04d Convert to synchronous resets 2015-10-09 22:36:58 -07:00
Alex Forencich
dbf720ffbe Improve 10G PHY TX timing performance 2015-06-23 07:43:06 -07:00
Alex Forencich
14a2caa994 Rework 10G ethernet MAC TX to add input register 2015-05-17 01:39:59 -07:00
Alex Forencich
15edfa0f85 Add missing initialize 2015-05-16 22:32:02 -07:00
Alex Forencich
bf349b16ba Add 10G MAC module 2015-05-08 00:05:21 -07:00