FPGA/verilog-ethernet
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2 Commits

Author SHA1 Message Date
Alex Forencich
ebc1c7ccc6 Rename checksum to calc_checksum in ip_ep 2014-09-25 16:26:23 -07:00
Alex Forencich
4bee0542b7 Add IP modules (8 bit datapath) 2014-09-19 17:35:51 -07:00